Possible to copy Intel 8755 with S4 ?

[Guest]

I have an S4, and need to replace a faulty 8755 on a piece of equipment. I have access to a 8755 with good 2kb memory. 8755 is not on S4 supported device list, but wondered if just due to low demand. Does anyone know if/how this can be done with S4? If so, which of the S4 modules (40 pin adapter) is needed?

Thanks in advance.

Martin Thiel

[Guest]

8755 8355

I've find things to contribute to the revovery of data contained in 8755 .

-It's not a MCU but a peripheral interface with IO capabilities. 8355 is
OTP, 8755 Erasable programmable. It have 2k*8 data
- the pins config from chipdir, i'vent find data page on Intel web server
8755
+--------\/--------+
1 -|prog&/ce vcc|- 40
2 -|ce pb7|- 39
3 -|clk pb6|- 38
4 -|reset pb5|- 37
5 -|vdd pb4|- 36
6 -|ready pb3|- 35
7 -|io/m pb2|- 34
8 -|/ior pb1|- 33
9 -|/rd pb0|- 32
10 -|/iow 8755 pa7|- 31
11 -|ale pa6|- 30
12 -|ad0 pa5|- 29
13 -|ad1 pa4|- 28
14 -|ad2 pa3|- 27
15 -|ad3 pa2|- 26
16 -|ad4 pa1|- 25
17 -|ad5 pa0|- 24
18 -|ad6 a10|- 23
19 -|ad7 a9|- 22
20 -|vss a8|- 21
+------------------+

- It's a peripheral which was used by 8085CPU. This cpu use address latch
enable (ALE pin 11) to strobe low A0-A7 address bit in 8755.(internal address
latch from 1983 Intel info book).
- pin 1 prog & /ce i suppose ce low enable cheap and high Vpp to prog
- pin 2 ce suppose /ce and ce the two are in use and inverted
- pin 3 clk from 8085 programming book, this clock is twice x1 x2 cristal
8085 clock.
- pin 4 reset to reset the chip (usualy it is low who reset the chip)
- pin 5-40-20 vdd vcc vss
- pin 6 ready , on 8085 it is a signal to go to cpu to signal chip is ready
(not used on 8085 prog)
- pin 7 io /m i suppose io for high=1 and low=0 for memory
- pin 8-10 /ior /iom for io not in use in that case suppose hight +5v with
resistor
- pin 9 /rd active low=0 read chip (prog=Vpp writte memory?)
- pin 11 ale strobe at the beginning of T cycle , that strobe A0-A7 in 8755
latch, on the falling edge of ale. Ale=0 then up, then low=0.
- Ad0-Ad7 at first T cycle (T1 address latch ) at T2 cycle read, T3 writte

This peripheral need buffers and circuitry to be read.
Trust this info and die. Use at your own risk.

philippe hunter